1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous Dynamic Random Access Memory (DRAM) semiconductor device having a data latch circuit for outputting input data synchronized with a plurality of control signals.
2. Description of the Related Art
Among synchronous dynamic random access memory (SDRAM) semiconductor devices, a double data rate (DDR) SDRAM semiconductor device includes a data latch circuit. The data latch circuit synchronizes input data with a control signal and a clock signal and outputs the synchronized input data.
FIG. 1 illustrates a synchronous DRAM semiconductor device including a data latch circuit. Referring to FIG. 1, a synchronous DRAM semiconductor device 101 includes a data latch circuit 11 including first through fifth flip-flops 61 through 65, respectively, and first, second, and third buffers 21, 41, and 51, respectively.
The first buffer 21 buffers an external control signal DQS, e.g., a data strobe signal, and generates a first internal control signal DQS_internal.
The second buffer 41 buffers an external clock signal CLK and generates an internal clock signal PCLK.
The third buffer 51 buffers external data DQ and outputs data input into the data latch circuit.
The first flip-flop 61 of the data latch circuit 11 synchronizes data received from the third buffer 51 with the rising edge of the internal control signal DQS_internal and outputs the synchronized data to the third flip-flop 63. The second flip-flop 62 synchronizes data received from the third buffer 51 with the falling edge of the internal control signal DQS_internal and outputs the synchronized data to the fifth flip-flop 65. The third flip-flop 63 synchronizes data received from the first flip-flop 61 with the falling edge of the internal control signal DQS_internal and outputs the synchronized data to the fourth flip-flop 64. When data is transmitted from the third flip-flop 63 to the fourth flip-flop 64, another data is simultaneously transmitted from the second flip-flop 62 to the fifth flip-flop 65. The fourth and fifth flip-flops 64 and 65, respectively, are synchronized with the rising edge of the internal clock signal PCLK and outputs data received from the second and third flip-flops 62 and 63, respectively. When the second and third flip-flops 62 and 63 output data to the fourth and fifth flip-flops 64 and 65, respectively, the first flip-flop 61 receives new data from the third buffer 51.
The data latch circuit 11 receives data from the third buffer 51 in synchronization with the rising and falling edges of the internal control signal DQS internal from the first buffer 21 and the rising edge of the internal clock signal PCLK. The data latch circuit 11 outputs even and odd data, DIN_E and DIN_O, respectively. Since the external control signal DQS and the internal clock signal PCLK have the same frequency, the frequency of each of the two data DIN_E and DIN_O becomes half the frequency of the data received from the third buffer 51, but the amount of the data output from the data latch circuit 11 is unchanged.
FIG. 2 is a timing diagram of the signals used in the data latch circuit 11 shown in FIG. 1. Referring to FIG. 2, the internal control signal DQS_internal is a signal generated by delaying the external control signal DQS for a first predetermined time interval, and the internal clock signal PCLK is a signal generated by delaying the external clock signal CLK for a second predetermined time interval. The time interval tCC indicates the frequency of the internal clock signal PCLK, and t1 and t2 indicate shift tolerance ranges to which the internal control signal DQS_internal can be shifted with respect to the internal clock signal PCLK. The time interval t3 indicates a design margin required for the design of a semiconductor device 101. The time intervals t4 and t5 indicate design factors considered as error ranges required for the design of the semiconductor device 101. The time interval t6 indicates a valid data window, that is, a range in which the internal clock signal PCLK can substantially latch data.
FIG. 3 is a diagram illustrating a synchronous DRAM semiconductor device including 4 data latch circuits. Referring to FIG. 3, data latch circuits 311 through 314 of a synchronous DRAM semiconductor device 301 each have one internal control signal, e.g., DSO_DS3. Thus, 4 internal control signals are needed for the four data latch circuits 311 through 314.
In the synchronous DRAM semiconductor devices 101 and 301 shown in FIGS. 1 and 3, respectively, the clock buffer 41 generating the internal clock signal PCLK internally makes and uses a short pulse for the purpose of obtaining a sufficient design margin. The control buffer 21 generates a pulse having the same duty cycle as the external control signal DQS. The internal clock signal PCLK is commonly input into the four data latch circuits 311 through 314. The internal control signal DQS_internal, however, is input into the four data latch circuits 311 through 314 along different paths. Thus, the line load between each of the four data latch circuits 311 through 314 differs. Accordingly, the structure and size of the clock buffer 41 are different from those of the control buffer 21. As a result, there is a difference between the time taken to generate the internal control signal DQS_internal after the external control signal DQS is input into the control buffer 21, the time taken to generate the internal clock signal PCLK after the external clock signal CLK is input into the clock buffer 41, and the time taken for each of the signals to reach the data latch circuit 11. In addition, since the above signals are affected differently by changes in process, voltage, and temperature, the time difference might further increase. As described above, since the time when the internal control signal DQS_internal occurs and the time when the internal clock signal PCLK occurs differ, the valid data window t6 decreases.
The phenomenon described above occurs more severely in high frequency semiconductor devices using high frequency signals. Thus, the line load of the internal control signal DQS_internal and the internal clock signal PCLK are designed to be about the same. In the synchronous semiconductor device including the four data latch circuits 311 through 314, four internal control signals must be designed to latch 32 input data, 8 input data each data latch circuit. However, to make the line load of each of the internal control signals the same as the line load of the internal clock signal PCLK, capacitors must be added to every path of the internal control signals, thereby increasing the area of the device.
It is an object of the present invention to overcome the disadvantages associated with prior art semiconductor devices.
It is another object of the present invention to provide a synchronous DRAM semiconductor device that is capable of maximizing a valid data window and minimizing an increase in the area of the device.
Accordingly, to achieve the above object, there is provided a synchronous DRAM semiconductor device including a first buffer adapted to generate a first internal control signal by buffering an external control signal. A second buffer is adapted to generate a second internal control signal by buffering the external control signal. A third buffer is adapted to generate an internal clock signal by buffering an external clock signal. A data latch circuit is adapted to receive external data and generate output data responsive to the first and second internal control signals and the internal clock signal.
A phase of the second internal control signal lags a phase of the first internal control signal.
The second and third buffers might have identical structures.
The data latch circuit includes first and second flip flops adapted to commonly receive internal data responsive to the first internal control signal. A third flip flop is adapted to receive data output from the first flip flop responsive to the second internal control signal. A fourth flip flop is adapted to receive data output from the second flip flop responsive to the second internal control signal. A fifth flip flop is adapted to receive data output from the third flip flop responsive to the internal clock signal. And a sixth flip flop is adapted to receive data output from the fourth flip flop responsive to the internal clock signal. The third and fourth flip flops might operate responsive to a falling edge of the second internal control signal. The fifth and sixth flip flops might operate responsive to a rising edge of the internal clock signal.
The data latch might alternatively include a first and second flip flops adapted to commonly receive internal data responsive to the first internal control signal. A seventh flip flop is adapted to receive data output from the first flip flop responsive to first internal control signal. A third flip flop is adapted to receive data output from the seventh flip flop responsive to the second internal control signal. A fourth flip flop is adapted to receive data output from the second flip flop responsive to the second internal control signal. A fifth flip flop is adapted to receive data output from the third flip flop responsive to the internal clock signal. And a sixth flip flop is adapted to receive data output from the fourth flip flop responsive to the internal clock signal. The third and fourth flip flops might operate responsive to a falling edge of the second internal control signal. The fifth and sixth flip flops might operate responsive to a rising edge of the internal clock signal. The seventh flip flop is synchronized with a falling edge of the second internal control signal.
A load of the second internal control signal from the second buffer to the data latch circuit is identical to a load of the internal clock signal from the third buffer to the data latch circuit.
A path of the second internal control signal from the second buffer to the data latch circuit is identical to a path of the internal clock signal from the third buffer to the data latch circuit.